As is well known in the electrically erasable programmable read-only memory (EEPROM) art, the erasing and writing operations within an EEPROM require a voltage which is larger than that required for the read operation. During a write or erase operation, the Fowler-Nordheim effect is utilized to cause electrons to tunnel through a thin oxide layer and to be stored on the floating gate of the memory cell, in the case of an erase operation; or to be depleted from the floating gate, in the case of a write operation to a logic zero. A voltage of between 20 and 25 volts is required to produce the Fowler-Nordheim effect.
In early EEPROM devices, an external high voltage source was required to provide the high voltage level for writing and erasing. These high voltage sources typically took the form of a separate, external high voltage power source, or some form of step-up circuitry.
More recently, voltage multipliers have been built into the EEPROM devices by which the nominal supply voltage, Vcc, is multiplied up to the required internal high voltage level, Vpp. These internal voltage multipliers typically comprise a chain of diode/capacitor combinations which rectify some periodic pulsewave form and additively accumulate the rectified voltages. One limitation of such internal high voltage generators is that the maximum current typically available therefrom is approximately 10 microamps. This presents a severe limitation on permissible current demand during an erase or write operation in the EEPROM.
The Vpp voltage is typically applied to the word lines corresponding to the cell being erased, or written into, by way of decoder circuitry. In the past, these decoder circuits have typically drawn current from the Vpp supply even when the decoder was not addressing the word line. One such decoder of the prior art employed NOR gates in a pull-up mode. In such a configuration, a depletion pull-up transistor provides a signal path between the Vpp supply line and the word line to be selected. A plurality of enhancement transistors are connected between the word line and ground to provide a current sink path. When the corresponding word line is addressed, the gate terminals of the plurality of enhancement transistors are all set to a logic zero. This, disables all of the current sink paths and permits the word line to be pulled up to the Vpp level. However, as long as one of the gate terminals of the plurality of enhancement transistors is at a logic one, such as when the corresponding word line is not being selected, a current sink path is provided which sinks DC current from the Vpp supply.
As is clear from the above discussion, there exists a need for a method and apparatus for applying the internal Vpp to selected word lines such that word lines which are not selected do not draw current from the Vpp supply, and which minimize current demand from the Vpp supply in un-selected word lines.